Semiconductor devices in the form of integrated circuit chips (ICs) must typically be mounted on a flat surface such as a printed circuit board when they are incorporated into a product such as a computer or cellular phone. No surface-mount semiconductor packaging technology exists today that is capable of meeting the needs of the next-generation of discrete power semiconductor devices and Ics.
Such surface-mount power packages should include at least the following features:
1. A low electrical resistance. PA1 2. The capability of shunting current and reducing the lateral resistance in a device's metal interconnect. PA1 3. A low thermal resistance. PA1 4. The capability of achieving high currents vertically (through backside) or laterally (topside). PA1 5. High manufacturability. PA1 6. A low intrinsic material cost. PA1 7. A low manufacturing cost. PA1 8. Reliable operation in power applications. PA1 9. The ability to acilitate at least three (and preferably more) isolated connections to the semiconductor. PA1 10. A low profile (height) and small footprint. PA1 it exhibits a large wire resistance; PA1 it suffers from a high thermal resistance; PA1 the down bonds needed for vertical devices introduce additional wire resistance; PA1 the down bonds limit the maximum die size of die, further increasing on-resistance; PA1 lateral spreading resistance across the die surface is large; and PA1 source bonding angles are restricted. PA1 the source bond wire resistance is high, especially from a limited number of wires; PA1 the number of uncommitted pins is low since half the pins are tied to the die pad; PA1 lateral spreading resistance across the die surface is large; and PA1 source bonding angles are restricted. PA1 the number of uncommitted pins is low since half the pins are tied to the die pad and most of the other pins are dedicated to the source; PA1 lateral spreading resistance across the die surface is large; PA1 the source bond resistance, while lower, is still not negligible; and PA1 source bonding angles are restricted.
Power semiconductor devices and ICs come in two types, those that conduct high currents because they exhibit low on-state voltage drops (and hence low power dissipation) and those that conduct "high" currents because they dissipate large amounts of power. Because of the varied use, construction, and operation of such power devices, the first two features listed (i.e. low electrical resistance) can be achieved in lieu of the third feature (low thermal resistance), but ideally one package should offer both low electrical and thermal resistance.
The fourth feature, a high current flow laterally or vertically, specifies that a power package should ideally be applicable to both lateral and vertical power devices, but at least one of the two orientations should be high current capable.
Of course, the package must be highly manufacturable since power transistors are used in high quantities, billions of units yearly, worldwide. Any a intrinsic manufacturing repeatability or yield problem would have dire consequences for the supplier and likely the user of such devices.
Another feature is low cost, including the package material cost and the cost of its manufacture. Of these, the material cost is fundamental since the price of certain materials such as gold wire, plastic molding, copper leadframes, etc., are based on the world market for the raw material and cannot be substantially changed through simple increases in semiconductor product volume. Package designs using smaller amounts of material are inherently cheaper to produce.
The reliability of a package in a power application means it must survive operating conditions commonly encountered in power device use, such as current spikes, higher ambient temperatures than normally encountered, significant self heating, thermal shock from repeated thermal transients, etc. Repeated pulses of current or heating can provoke fatigue-related failures, particularly at metallurgical junctions and interfaces. Fewer interfaces are preferable.
Two terminal packages are needed for diodes, transient suppressors, and fuses, while packages supporting at least 3 connections are useful for discrete transistors. Four connections up to 8 connections are extremely valuable for a variable of smarter power semiconductor components. Beyond 8 distinct connections, the use of such power package technology is concentrated on power integrated circuits.
Low profile surface mount packages, while not universally required, make it convenient for PC board manufacturing since power devices packaged in low profile packages have the same characteristics of other ICs on the same board and hence avoid the need for special handling. In some cases like battery packs, PCMCIA cards and cell phones, the low profile package may be crucial in meeting a critical thickness in the final end product.
Small footprint is generally a matter of overall product size, especially in portable electronics where size is an important consumer buying criteria--the smaller the better.
In a related consideration, the smaller the package footprint is on the board and the larger the semiconductor die it contains, the performance for a given size is greater.
While these goals may seem obvious, the fact is that today's power semiconductor-packaging technology does not meet these needs adequately, cost effectively, and in some cases, at all.
Present Surface Mount Package Approaches
FIG. 1 describes the process flow for the manufacture of a conventional prior-art surface mount package, such as the 8-pin small-outline (SO-8) package originally developed for ICs, or the ubiquitous 3-pin small outline transistor (SOT23) package. The flow starts with one or more semiconductor dice, a metal leadframe, and conductive epoxy or solder to attach the dice to the leadframe in an area known as the die pad. The assembly is then wire-bonded, connecting the metal "posts" of the package to the aluminum bonding pads on the device or IC with gold (or in some cases aluminum) wire. The bonding uses a thermo-compression or ultrasonic technique to achieve a good electrical connection and sufficient mechanical strength to withstand the subsequent manufacturing steps and operating conditions. After wire-bonding, the leadframe, still held together by a series of metal straps or tie-bars, is placed in a mold and subsequently injected with hot liquid plastic, also known as molding compound.
After the plastic cools, it provides mechanical rigidity to the bond wires, the die pad, and the package leads, so that the external leads can be clipped from any tie bars, thereby separating the unit from any others which may have been manufactured on the same tie bar.
Finally the leads are bent into their final shape. The bending process requires "clamping" the leads so that undue mechanical stress is not placed on the plastic package which could lead to cracking of the plastic.
FIG. 2 illustrates the prior art leadframe 10 comprising a repeated cell 11 (with die pad 12 and lead-assembly 13A and 13B) repeated 5 to 25 times in a strip. The strip comprises three tie bars that hold the repeated cells together in the strip until later separated after plastic injection molding has occurred. The tie bars comprise two outer tie bars 14A and 14C, holding the package leads 15A and 15B in place, and an inner tie bar 14C that holds the die pad 12 secure during the assembly process. The actual number of pins may vary depending on the package, with 3-, 6-, 8-, 14- and 16-pin packages being commonly employed. An end-piece 16 (located on each end) holds the entire strip together during manufacture, by securing tie bars 14A, 14B, and 14C.
FIGS. 3A-3G illustrate cross sectional views of the steps of the flow described in FIG. 1.
The leadframe 10 in FIG. 3A includes the center die pad, and two of the leads 15A and 15B. In FIG. 3B, the semiconductor die 17 is attached (using a thin layer of solder or epoxy not shown) to the die pad 12. The die-attach operation is then followed by wire bonding in FIG. 3C. For each of the bond wires 18 the ball bond 19 (the first bond performed) is present on the die, and the wedge bond 20 (the last bond for each wire) is present on the lead (also called the post). The wedge bond occurs where the wire is cut. The difference between the shape of the ball bond and the wedge bond is characteristic of the wire bonding machine's operation. The wedge bond is preferred on the leadframe 15A and 15B to avoid the risk of damage to the semiconductor from the stress associated with the wire cutting.
In FIG. 3D, the plastic 21 is injected (shown by a dotted line) to cover each die 17 and its associated bond wires 18 and leads 15A, 15B as shown in the top view of FIG. 3E. The tie bars 14A and 14B are intentionally left uncovered. A portion of tie bar 14C is covered by the plastic but the most of tie bar 14C remains uncovered. After trimming, the individual packaged die and its separate leads are held together by the plastic. The tie bars 14A and 14B, along with a small portion of leads 15A and 15B are cut away by a mechanical cutting machine, thereby separating the final packaged product 11 from others on the same strip. The tie bar 14C connected to the die pad 12 is trimmed flush with the plastic package outline 21. Finally, the leads 15A and 15B are bent for surface mounting as shown in FIG. 3G.
FIG. 4A illustrates the size restrictions in a conventional prior-art SO-8 package mounted on printed circuit board (PCB) 22. Design rules are chosen to achieve both high manufacturability and reliability. For example the design rule X1, the minimum allowable plastic above the top of the bond wire, must guarantee that any bond wire 18 does not become exposed, i.e. protrude through the plastic, under any circumstance during manufacturing. The wire bond height X2 is especially restrictive in setting the minimum possible height of the package, since it must have a sufficient loop height to prevent accidental shorting from bond wire 18 to the edge of the silicon die 17 or to die pad 12. Table 1 below defines some typical values for each dimension.
TABLE 1 Value Rule Design Rule Description (mm) Failure Mode X1 Minimum plastic above top of wire 0.08 Prevent exposed wire (on top) X2 Wire loop height 0.13 Avoid wire short to die edge X3 Chip thickness 0.28 Thin without breaking X4 Lead frame thickness 0.2 Minimize lead resistance X5 Minimum plastic below leadframe 0.08 Prevent exposed die pad X6 Plastic clearance above board (standoff) 0.15 Lead (not plastic) must touch PCB XT Total package height (profile) 1.7 Minimize package thickness Y1 Minimum lead foot Lead must land on PCB pad Y2 Minimum extension of lead past plastic Need room for lead clamp Y3 Minimum plastic enclosure of wire Prevent exposed wire (on side) Y4 Minimum post foot width for bonding Need room for wire wedge bond Y5 Minimum die pad to lead space 0.25 Avoid lead to die pad short Y6 Space of die inside die pad 0.13 Avoid chip overhang & breakage Y7 Bond depth inside of chip edge 0.10 Avoid die edge cracking YW Max lateral dimension of wire length 1 Avoid high wire resistance & sag YC Maximum die dimension (narrow direc) 1.3 Maximize die area YT Total lead to lead board footprint Minimize package board area The actual board dimension required by the package is given by YT = YC + 2 .multidot. (Y6 + Y5 + Y4 + Y3 + Y2 + Y1) XT = X6 + X5 + X4 + X3 + X2 + X1
where the YT is the narrow direction of the package.
The design rule Y7 is determined by the edge construction of the die needed to avoid die cracking due to bonding and to allow a die edge termination or scribe seal (to prevent ionic contamination from leaking into the die), as shown in FIG. 4B. In the example shown, a silicon die having a P-type substrate 31 is die-attached to the package die pad 30. The die pad and leadframe may be copper but typically are constructed out of lower cost Alloy-42, a nomenclature common to the packaging industry. The substrate contains a region of high P-type concentration 32 (referred to as P+) and another region of heavily doped N-type material (N+) 33 biased at a potential dissimilar to the P-substrate 31 and P+ region 32. A space 40 separating N+ region 33 and substrate-connected P+ region 32 is needed to support the voltage difference between these regions. The N+ region 33 is contacted by a contact opening 34 in a glass or oxide layer 38 and covered with a bond-pad area metal layer 35. P+ region 32 is also contacted by opening 36 which extends to the chip edge 41, a portion of which is contacted by metal layer 37. The surface is covered by a glass or silicon nitride passivation layer 39 except where openings are necessary to expose bonding pad areas such as exposed metal 35. The bond pad is attached to a bond wire 42, typically made of gold or aluminum. Ball bond 43 occurs at the point of wire bonding.
The design rule Y7 is needed to prevent electrical failures due to shorts between N+ region 33 and bond wire 42 with the P-substrate 31. For example if bond wire 42 accidentally shorts to die edge 41 or P+ region 32, an electrical failure will result. Likewise, ball bond 43 must not crack passivation layer 38 or 39 and create a short to metal 37. The sawed silicon edge 41 cannot be allowed to crack the silicon or intrude into region 40, or else it will cause a failure. While the Y7 rule varies from one device to another, it reduces the amount of usable silicon that can be devoted to active device structures. This region can then be referred to as the "edge termination" of the device or integrated circuit. It can vary in dimension from 0.025 mm to 0.250 mm depending on the type of chip, its technology, and the maximum voltage of the device or IC being assembled.
In the package shown in FIGS. 2-4, the percentage of the PCB area that is actually utilized by active silicon can be quite small, as low as 25% in small packages. The low area utilization occurs from wasted space resulting from mechanical design rules such as rule Y5 and Y6. Moreover, electrical contact to the backside of the silicon die and the die pad are assumed to occur through a topside contact in the silicon. While such an approach may be satisfactory in low current ICs, in vertical discrete ICs and vertical power MOSFETs, a substantial current can occur vertically into the die pad. Wire bonding to the die pad further reduces the usable die pad area and hence the active silicon area. Wire bonds also introduce additional series resistance into the package.
FIGS. 5A-5G offer a series of cross-sectional and top views of a prior art package that is better suited to vertical power devices than the package shown in FIG. 3. Specifically, FIG. 5A illustrates a modified leadframe 50 that is an improvement on a conventional leadframe, enhancing its power dissipation and eliminating the need for wire bonds to connect to the backside of the silicon die. In this prior art design, multiple leads 59 extend directly from the die pad 52 to the outside of the package without the need for bond wires. The combination of die pad 52, leads 59, and tie bars 54 and 55, together comprise assembly 56A. The other assembly 56B is composed of leads 58 and tie bar 57 as in the aforementioned conventional leadframe 10. The entire unit cell 51 is repeated at regular intervals and held together by an end piece as in the previous leadframe example. It should be noted while assembly 56A merges leads 59 into die pad 52, the assembly appears as though die pad 52 is larger and "holes" 53 have been cut out of the die pad.
Furthermore, it should be clarified that such a design is normally only useful in vertical power device packaging since half the available leads are dedicated (shorted) to the substrate connection. The reduced number of uncommitted pins makes such a package less useful for integrated circuits where a large number of electrical connections may be needed.
In FIG. 5B, a vertical power device 60 is attached with solder or conductive epoxy to the leadframe assembly 56A in die pad area 52, followed by wire bonding in FIG. 5C. Each wire bond 61 comprises a ball bond 62 and a wedge bond 63, normally with the wedge bond landing on the leadframe, not the silicon die 60. Only one set of wires can be (or need be) bonded since the leads on the opposite side of the package are tied to the die pad. In FIG. 5D, the plastic 64 is injection-molded, as further described in the top view drawing of FIG. 5E. Since one set of bond wires is eliminated in the path of current, the package resistance is thereby reduced in vertical current flow devices. FIG. 5F shows an individual die and unit cell 51 after it and its package are trimmed from the leadframe and tie bars. FIG. 5G illustrates the same device after lead bending.
FIGS. 6A-6C illustrate and define the terminology of the electrothermal characteristics of surface-mount-packaged semiconductor components, characteristics important in comparing power semiconductor devices. In the schematic of FIG. 6A, a power MOSFET 70 is electrically in series with a source resistance 71 having a value R.sub.S and a drain resistance 72 having a resistance R.sub.D. The value of R.sub.S varies primarily with the number of bond wires used, depending on the space available within the package. R.sub.S ranges from 50 m.OMEGA. (using one minimum sized wire bond) to at the lowest 4 m.OMEGA. when using as many as sixteen bond wires. The drain resistance R.sub.D is identical to R.sub.S in the conventional packages shown in FIG. 2. In power packages such as the one shown in FIG. 5, the drain resistance is simply the copper leadframe resistance, typically a fraction of a milliohm.
FIG. 6A also illustrates the thermal characteristics of a semiconductor schematically where the MOSFET 70 is a heat source releasing heat into the ambient and into printed circuit board (PCB) 73. Heat released directly from the plastic package into the ambient occurs mostly by convention and has a thermal resistance R.THETA.ja in the range of 160.degree. C./W. or even higher. The steady state conduction of the heat from the package into the board depends on the package design. In a conventional package, heat conduction must occur from the die into the leadframe via only the bond wires. The thermal resistance from the "junction" to the board R.THETA.jb is around 80.degree. C./W. Assuming the convection from the PCB to the ambient has a thermal resistance R.THETA.ba of around 35.degree. C./W., the total thermal resistance of the conventional package is then around 115.degree. C./W. Using the power package design of FIG. 5, the thermal resistance from the "junction" to the board R.THETA.jb is improved to approximately 20.degree. C./W., for a total junction to ambient thermal resistance of 55.degree. C./W. While this is not as low as needed (ideally in the range of 1.degree. C./W.) it is a substantially better than the traditional IC package.
FIG. 6B illustrates a commercial data sheet curve of thermal resistance versus the duration of a pulse of power (in seconds), for single and repeated pulses. The thermal resistance is normalized to the steady state (continuous power dissipation) thermal resistance value. Unity is therefore the same as continuous operation. Note that the thermal resistance is lower than the steady state value during short pulses of power because the silicon itself absorbs some of the heat. Around 2 milliseconds, the change in slope of the curve reflects the influence of the backside of the die and the die attach, meaning the heat traveled (diffused) through the entire silicon wafer before it reached the leadframe. At approximately 1 second, the printed circuit board, the ambient, and thermal convection come into play. If heat could be extracted sooner the performance of the die would improve during high power pulsed operation. A lower thermal resistance package is needed to improve the continuous power dissipation of the package.
Self-heating raises the temperature of the silicon by an amount given by the expression EQU .DELTA.T=P.multidot.R.sub..THETA.ja
where a rise in temperature may in turn increase the resistance of the MOSFET. Depending on the circuit, an increase in resistance can lead to a further increase in power dissipation and more self-heating.
The package resistance also places a limit on the maximum useful die size for a power device. FIG. 6C illustrates the on resistance versus die size of four different power MOSFET technologies, labeled by their specific on-resistance (i.e. the resistance-area product) as 3, 1, 0.3, and 0.1 m.OMEGA.cm.sup.2. Technologically, 3.0-m.OMEGA.cm.sup.2 represents a device and process technology several years ago (circa 1992), while 0.1 m.OMEGA.cm.sup.2 is more advanced than state-of-the-art devices today. The ideal silicon resistance, illustrated by the thin curves labeled B, D, G, and H, follows a hyperbolic curve given by the relation ##EQU1##
The package resistance, labeled as R.sub.package, is shown constant at 3.5 m.OMEGA.. The total resistance of the product curves A, C, E and F shows an asymptotic behavior limited to a minimum value determined by the package resistance by the relation ##EQU2##
While the package resistance had a negligible influence on products several generations ago, new silicon power MOSFET technology is now compromised by high package resistance. Silicon device areas over 1 to 1.5 mm.sup.2 deviate substantially from their ideal performance values. For example for a 0.1-m.OMEGA.cm.sup.2 MOSFET technology and a 10-mm.sup.2 die, the silicon resistance is 1 m.OMEGA. (curve H) while the packaged die is 4.5 m.OMEGA. (curve F), more than four times the silicon value. The increased on-resistance lowers efficiency and increases self-heating in the device, further degrading its performance.
FIGS. 7A-7F illustrate a variety of prior-art vertical power devices requiring power-packaging technology. In FIG. 7A a vertical planar DMOSFET is shown in cross section. Starting with a heavily doped (N+) substrate 81, an epitaxial layer 82 is grown to a thickness of 2 to 20 um (depending on the target breakdown of the device). P-type body region 83 and N+ source regions 84 are then implanted and diffused, generally self-aligned to a polysilicon gate 86. The polysilicon gate 86 is separated from the underlying silicon by a thin gate oxide layer 85 having a thickness of 100 to 1000 .ANG.. The gate (and the entire device) is also generally covered in a glass to avoid shorting to overlying source metal 88. The glass is removed in locations between the gate regions forming contact windows 87 whereby the source metal 88 is able to contact N+ source regions 84 and, through P+ region 89, P-type body regions 83.
The operation of the device involves impressing a voltage on gate 86 so as to invert the P-type body region located on the planar surface of the silicon under the gate, and allow channel conduction between the source 84 and the epitaxial drain 82. As illustrated by the dotted lines, the current flows laterally along the planar surface of the device through the double-diffused channel of the device (hence its name "planar" DMOSFET). Once through the channel, the current then turns and flows vertically to the backside, expanding in area till the epitaxial conducting region abuts current conduction in an adjacent cell. To package such a device, a low resistance path must be available both on the surface and on the backside of the device. The gate must also be connected to the surface. So unlike a P-N diode, one side needs at least two electrical connections, one of which must carry high currents.
FIG. 7B illustrates a trench gated vertical power MOSFET 90, similar to planar DMOSFET 80, except that the gate is embedded in a trench etched in the silicon surface. In this device, epitaxial layer 92 is formed on N+ substrate 91, followed by the formation of the trench gate. The trench gate is a region where the silicon is removed via photomasking and reactive ion etching, followed by formation of the gate oxide layer 95, and filling with the polysilicon gate 96 so that a nearly flat surface results. The flat surface occurs from overfilling the polysilicon, then etching it back near the top of the trench. The P-type body region 93 is then formed within the silicon mesa located between adjacent trenches. N+ source and P+ body contact implants are formed within P-type body region 93. A glass is generally deposited over then entire surface after which a contact window 97 is then etched to expose and electrically short the N+ source region 94 and P+ region 97 to the topside metal layer 98. Operation is similar to planar DMOS 80 except that channel conduction occurs vertically alongside the sidewall of the trench.
FIG. 7C illustrates the plan view of either vertical planar DMOSFET 80 or trench gated DMOSFET 90. Most of the device is covered by a source metal layer 100. Gate pad 101 is another metal region electrically isolated from the source by 2 to 15 um of spacing. The outer edge of the device also includes a metal ring 102 shorted to the drain potential, referred to as an equipotential ring or EQR, primarily introduced for purposes of achieving improved reliability against ionic migration. This outer ring is a source of risk for an accidental short between the source or gate connections during assembly. The silicon also extends beyond this ring by another 20 to 70 um, to the location indicated by the dashed line 103. The protruding silicon varies in dimension due to the sawing process when the wafer is cut into separate dice. This area of the die is also biased at the drain potential and may short to a source or gate connected bond wire during packaging.
In FIG. 7D, a metal gate finger 104 runs down the center of the device splitting source metal 100 in half except at the end of the finger. Package connections (e.g. bond wires) are therefore required to be made to both halves of the source metal to prevent an increase in resistance of the device from packaging. The package connections place certain restrictions on the dimension and aspect ratio of the silicon die design. These restrictions are more exaggerated in the die design of FIG. 7E since the source metal 100 is divided into three sections by three gate fingers 104. Electrically the three source sections are still in parallel, but at high currents the lateral resistance of the thin metal layer 100 adds internal resistance to the device, thereby degrading its performance as a power switch.
In the device shown in FIG. 7F, a multi-donut-shaped gate metal 106 is employed to reduce signal propagation delay throughout the device. The resulting separation of the source metal into four completely isolated islands 105A, 105B, 105C, and 105D, demands electrical connections to each section through the package design and wire bond placement. Such a design may be incompatible with specific package pinouts. Wire bonding is especially problematic in such layouts since the location of the leadframe limits the location and angle of wire bonds.
For example, in FIG. 8, the source bond wire 113 attached to source metal 110, extends over EQR metal 111 which is intentionally shorted to the drain potential. In the example shown the EQR metal contacts outer polysilicon plate 113 that extends into the scribe-street between dice. During sawing, saw edge 117 cuts through polysilicon layer 113, silicon substrate 115 and epitaxial layer 116, shorting them together at the drain potential. The source metal 110, polysilicon field plate 112 and P-type diffusion 114 are biased at a high negative potential relative to the drain, thereby reverse biasing the junction formed between P diffusion 114 and N-type epitaxial layer 115. If wire 113 sags or is pushed (by molten plastic during the injection molding process) into EQR 1, the device will short and no longer be functional. Longer bond wires may help reduce the probability of the short, but add resistance to the device. This is one example where wire bonding involves tradeoffs and compromises between performance and manufacturability..
Wire bonding creates other complications in manufacturing, some which are manifest as yield loss, and others that may show up later as reliability failures. In FIG. 9b, a wire ball bond 120 located on top of the active trench-gated MOSFET transistors (similar to the construction of device 90 in FIG. 7B), can cause micro-cracks in the oxide or in the silicon. Such micro-cracks, too small to observe without an electron microscope, may irreparably damage the top oxide (glass) 121 covering the trench (e.g. defect A), or damage the gate oxide 95 that embeds the polysilicon gate (i.e. defect 13). In extreme cases, the micro-crack may extend into the silicon in the vicinity of the P-type body 93 to N-type epitaxial drain 92 (i.e. defect C) and cause junction leakage. In the worse case the micro-cracks may only become electrically active after the product has been shipped to a customer, and after the product has been operating for an extended time (a field failure).
If it is desirable to attempt the second bond, the wedge bond 125, on the silicon rather than on the leadframe, the potential damage to the semiconductor is worse. As shown in FIG. 9B, the process of forming the wedge bond 125 and the wire cut 126 produce lines of stress pushed into the top metal 98, and ultimately into the underlying silicon and oxide layers. Micro-cracks are likely to occur unless the pressure is accurately controlled. In manufacturing, tightly controlled mechanical processes require frequent machine calibration, monitoring and repair. Increased preventative maintenance and greater machine downtime lead to higher manufacturing costs.
One solution to the micro-crack problem is to bond over dedicated bonding pads rather than over active device areas. Avoiding bonding over active area leads to higher metal resistance since currents must be bussed to pad areas using thin traces of metal and usable silicon "real estate" is lost. Even so, a wedge bond requires a larger area than a ball bond because the machine needs more room to cut the bond wire. In FIG. 9C, the size of an isolated bond pad for a ball bond (e.g. a gate pad) shown by the dotted line 130 and surrounded by an unrelated metal 131 is compared to the shape of the same pad adjusted for a wedge bond. The wedge bond pad 132 and the surrounding metal 133 is rectangular, and roughly 50% longer in one direction. For example, a 2 mil (50 um) gold wire ball bond can be bonded to a pad 100 um.times.100 um in dimension, while the wedge bond requires a dimension of 150 um.times.100 um. In packages where two chips are connected by a bond wire (referred to as a chip-to-chip bond), one of the two bonds is necessarily a wedge bond.
Another problem characteristic of wire bonds is the possibility of a poor quality bond between the wire and the aluminum, especially in high current applications. In FIG. 9D, the attachment of ball bond 140 and aluminum pad 141 illustrates a poor quality attach at points A and B where the bond does not touch the metal uniformly. A high interfacial resistance and possibly a long-term reliability problem can result.
In over-current conditions such as momentary short circuit conditions, bond wires can fail in any number of unpredictable ways. In FIG. 9E, a bond wire 142 has melted at point A without melting the surrounding plastic 143. In FIG. 9F, a large current has melted the wire and surrounding plastic (around point B) exposing the wire 142 and producing byproducts of the melting process such as gases or deposits 144 that may be toxic. The melting process may in turn cause a fire, especially for power transistors mounted inside of battery packs where explosive chemicals are contained.
Still other failures in wire bonds occur gradually over time. Electromigration failures, such as the one shown at point C in FIG. 9G, occurs where the current density is higher than its surroundings (e.g. where the wire may have been accidentally crimped), and where gradually, the metal atoms are transported away further thinning the wire until it fails open.
Wire bonds are not the only "parasitic" elements of resistance limiting the continued reduction of power MOSFET on-resistance. The thin top metal of a vertical power MOSFET also contributes resistance to the device. Referring to FIG. 10A, a trench gate vertical power device mounted on leadframe 150 comprises a heavily doped substrate 151, an active epitaxial layer containing the trench-gated MOSFET devices, a thin metal layer 153 and a bond wire 154. Each region defines contributes to the resistance of the product. In the case of substrate 151 and epitaxial layer 152, the resistances occur in the direction of vertical current flow. In the leadframe 150, the current flow, while lateral (i.e. perpendicular to the silicon), exhibits little voltage drop because the copper has a very low resistivity and the leadframe is relatively thick (over 175 um or 1.75 mm). The top metal layer 153, however, is only 2 to 4 um thick, typically 50 times thinner. Since bond wire 154 does not cover the surface of the die, current emanating from thousands to tens of thousands of transistors must flow laterally at distances up to a millimeter before reaching the bond wire. The resistance R.sub.metal can contribute as much as a milliohm of resistance to the device. The resistance of the bond wire 154 contributes tens-of-milliohms per wire, but in parallel with a large number of wires (e.g. 15 bond wires) adds a total of a few milliohms.
Because of the lateral resistance of the top metal layer, the individual transistor cells are not actually in parallel. The schematic of FIG. 10B illustrates a finite lateral resistance 160 exists between adjacent MOSFET devices 161. The total source resistance increases with distance to the nearest bond wire. Unfortunately, 4 um of metal is already quite thick by IC processing standards (most ICs use metal thickness well below 1 um). Such thick layers take a long time to deposit, and are subject to cracking if it is deposited to too thick a value. Increasing the bond wire length to place the bonds more evenly across the surface of the device is likewise problematic, since it may reduce the R.sub.metal lateral resistance by increasing the wire resistance 162 by an amount equal than the reduction in lateral spreading resistance. Shown conceptually in FIG. 10C, any increase in the aspect ratio (the distance to the nearest bond wire divided by the distance between bond wires along the width of the chip), effectively compromises the benefit gained by adding more transistors in parallel. The resulting increase in the product's metal resistance, due to increased spreading resistance, eventually cancels any benefit in transistor resistance. As shown in curve for resistance (the curve corresponding to the graph's left y-axis), larger area devices with increasing aspect ratios asymptotically approach some minimum resistance. The on-resistance-area product (i.e. curve corresponding to the right y-axis) actually increases, making the device more expensive for the same performance.
FIGS. 11A-11E summarize some of the possible interactions between die layout and package design, considering all of the aforementioned bond wire related issues. In FIG. 11A, the problem of packaging a vertical power device with a conventional IC package (such as the one first described in FIG. 2) is exemplified. The device 170 has its backside drain connection to die pad 171 while its topside source is connected to pins 173 via bond wires 176. Its topside gate connection is wire bonded by wire 175 to pin 172. Because the leadframe 171 is not connected directly to drain pins 174, bond wires 177 are required as down-bonds from the drain pins to the die pad 171.
The packaged device of FIG. 11A suffers from numerous problems including:
In FIG. 11B, the down bonds have been eliminated by merging the drain pins into the die pad (as in the package of FIG. 5) to form a new die pad assembly 178, reducing package resistance, lowering thermal resistance, and facilitating a larger die area. The package of 11B still suffers from numerous limitations, namely:
In FIG. 11C, the number of source bond wires 176 is increased to fifteen. The extra wires are introduced by tying the three source pins together into a bus bar 180, thereby increasing the area available for wedge bonds on the leadframe. Otherwise this package's characteristics are similar to the package of FIG. 11B. Still, the package of FIG. 11C also suffers from numerous limitations, namely:
An example of the limitations in the source bonding angles of the package of FIG. 11C is shown in FIG. 11D. In a design of a die similar to FIG. 7F, the die 179 is partitioned into three isolated-source sections SA, SB, and SC. Source wire bonds into the SA section must cross the gate pad near gate bond wire 175, unacceptable for manufacturing.
Larger bonding wires do not reduce overall resistance either. As illustrated in FIG. 11E, the replacement of source bond wires 176 by larger diameter wires 182 (e.g. replacing 50 um wires by 75 um wires) results in a higher resistance since the number of wires is reduced. The gate pad also must be increased in size to accommodate the larger gate bond wire 181, further reducing active area.
Another package technology, albeit much more costly than the plastic surface mount packages described thusfar, is the TO-220 family of power packages shown in FIGS. 12A-12D. The material costs alone of these power packages exceed the entire product cost of many of the SO-8 type surface-mount products. Nonetheless, they have become established for their low thermal resistance, especially in the automotive industry.
In FIG. 12A, the TO-220 package comprises a die pad 191 that is also a heat slug and external mounting tab having a hole 198. Drain pin 192 is merged into the die pad 191 while source pin 193 and gate pin 194 are connected via bond wires 195 and 196, respectively. In high volume production designs, bond wires 195 and 196 are chosen to be the same size, typically 14 or 20-mil aluminum wire. The large source wire, if used for the gate contact, however, wastes area for its requisite oversized gate pad. Using two different sized wires means the assembly process requires multiple passes, adding cost to the overall packaging operation. As shown in FIG. 12B, the tab 191 covers the back of the package and extends beyond the plastic 197 but another 35% or more. Consequently, the area utilization of this package if surface mounted is lower than the SO-8, i.e., it wastes board space.
FIG. 12C illustrates a cross section of the device revealing the large portion of the tab not covered by plastic and not mounted to any silicon die. The extended portion of the tab does not substantially improve thermal or electrical resistance of the device and therefore is wasted area. The straight legged TO-220 of FIG. 12C is typically used in through hole constructions. Two variants, the similarly sized D2PAK and the smaller DPAK, have similar construction, except that the leads are trimmed short and bent onto the surface.
Other major limitations of this package are the limited number of bond wires it can accommodate, and even more so the limited number of pins it offers (typically a maximum of three to seven). Of its limited pins, the center pin 192 is redundant since it is electrically the same as the backside tab 191. So while the backside metal is a good concept its implementation in the TO-220 package family is not adaptable to modern low-cost packaging technology, and is especially not useful for higher pin count device s like power ICs.
FIGS. 13A-13E illustrate an alternative packaging technology, primarily innovated for high pin count applications, which eliminates bond wires through the use of large gold bumps formed on the surface of the wafer. This technology was applied in assembly methods historically referred to as flip-chip, bump, or tape automated bonding (TAB). To date, bump-packaging technology has not been successful in power device applications for a variety of reasons. As shown in FIG. 13A, numerous large gold bumps, 250 um or greater in height are grown on the silicon surface over open bonding pads. The bonding pads are defined by openings in the passivant layer 206 and underlying oxide layer 205.
Aluminum interconnection on the chip also provides the metal 201 in the bond pad area. Gold however is not easily deposited to large thicknesses, so it must be grown using electroplating or electroless plating. To grow gold over aluminum, an intermediate layer is required. Frequently, a thin layer of titanium 202 followed by nickel 203 and possibly gold or silver is evaporated on the die before deposition can begin. An extra masking step is generally needed to remove the metal between bonding pads to avoid shorts. Then growth of bump 204 can commence. Electroplating of gold is well known in the industry and will not be discussed further here.
As shown in FIG. 13B, once the bumps are grown, the bumped die can be attached using ultrasonic bonding to leadframe 207 and encapsulated by plastic 208. The leadframe as shown in FIG. 13C may be a metal leadframe, generally of a thin layer of a conductor 209 like copper patterned on an insulating tape 210 (hence its name tape automated bonding). The die is then bump attached to the leadframe. The leadframe and tape may in fact have several levels as shown in FIG. 13D. The finished assembly may likewise be coated with a passivant 211, or a silicone compound, or a polyimide to seal the product. Bumps 212 may also be formed on the outside of the assembly to attach it to the metal traces 213 on printed circuit board 214. Such a construction if frequently referred to as a ball grid array or micro-ball grid array. In other cases as shown in FIG. 13E, the die may be bumped directly onto the PCB by bonding the bumps 204 onto the board traces 213. In such cases the passivant 211 is needed to protect the die from ionic contamination.
The problem with bump and ball grid packages is their high expense and their relatively poor reliability, especially in power applications. The bump interfaces 202 and 203 suffer degradation during thermal cycling and power pulsing due to differences in the thermal coefficient of expansion of the various dissimilar materials. While the bump technology is bond-wireless, it is not a low cost high volume technology, and it does not support vertical conduction devices, so its use in power ICs is suspect and its applicability in vertical power discretes is very poor.
What is needed is a bond-wireless (BWL) package technology with low cost, high manufacturability, and high reliability similar to the SO-8 package construction but (ideally) with thermal resistance similar to the D2PAK. While some attempts have been made thusfar to introduce wire-free power packages, most suffer from similar problems including stress, die cracking, alignment, and co-planarity of multiple lead leadframes.